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MF1449-01
IEEE1394 Controller
S1R72900F00A S1R75801F00A
Technical Manual
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001, All rights reserved.
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All other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies.
The information of the product number change
Starting April 1, 2001 the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative.
Configuration of product number
qDEVICES
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S1
R
72900
F
00
A
Packing specification Specifications Shape (F:QFP) Model number Model name (R:Exclusive use controller, Peripheral) Product classification (S1:Semiconductors)
SPC7281F0A
Contents
1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. BLOCK DIAGRAM ............................................................................................................................................. 2 4. PIN LAYOUT ..................................................................................................................................................... 3 5. PIN ASSIGNMENT TABLE ................................................................................................................................ 4 6. PIN DESCRIPTION ........................................................................................................................................... 7 7. FUNCTIONAL DESCRIPTION .......................................................................................................................... 9
www..com 7.1 Control Register ......................................................................................................................................... 9
7.2 Data Format ............................................................................................................................................. 24 7.3 Cable Port Interface ................................................................................................................................. 27 7.4 Link Layer Controller Interface ................................................................................................................. 30 7.5 Oscillating Circuit ..................................................................................................................................... 42 7.6 Power Down ............................................................................................................................................. 42 8. ELECTRICAL CHARACTERISTICS ................................................................................................................ 43 8.1 Absolute Maximum Ratings ..................................................................................................................... 43 8.2 Recommended Operating Conditions ...................................................................................................... 43 8.3 DC Characteristics ................................................................................................................................... 44 8.4 AC Characteristics ................................................................................................................................... 47 9. EXAMPLE OF EXTERNAL CONNECTION ..................................................................................................... 49 10. OUTLINE DIMENSIONS ................................................................................................................................. 50
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Rev. 1.0
S1R72900F00A
1. DESCRIPTION
The SIR72900F00A is a physical layer IC compliant with the IEEE 1394-1995 and IEEE 1394a-2000 standards. With the two 1394 ports, the SIR72900F00A supports transmission speeds of 400/200/100 Mbit/sec. The product incorporates a 400-MHz PLL, reference voltage generating circuit, high-speed transceiver, LINK layer interface, and a state machine circuit for bus initialization and arbitration.
2. FEATURES
* Complies with the IEEE 1394-1995 and IEEE 1394a2000 standards. * Supports transmission speeds of S400 (393.216 Mbit/ sec), S200 (196.608 Mbit/sec), and S100 (98.304 Mbit/sec). * Incorporates a 400-MHz PLL for transmission at S400/S200/S100 and 50-MHz SCLK output. * Offers independent TpBias output for each port. * Supports the Cable Power Status function that detects a cable power drop. * Supports DC and AC connections of the PHY/LINK interface. * Built-in oscillating circuit * High-accuracy, low-amplitude differential high-speed transceiver * Bus initialization, arbitration, port connection, and control state machine circuits * PHY/LINK interface circuit * High-speed DS encoder * Supports the short bus reset function at detection of LINK layer IC power-off. * Single 3.3-V power supply * 64-Pin Plastic QFP * Designed with the low-power CMOS technology. * This product is not radioresistant.
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Rev. 1.0
EPSON
1
S1R72900F00A
3. BLOCK DIAGRAM
Cable Power Status
CPS
LPS
DS-Link Encoder/Decoder
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TpBias1
TpBias Gen.
LREQ CTL[0:1] D[0:7] BCLKON
Link Interface
TpBias2
VoltageCurrent Gen
R1 R0 TpA1 TpB1 TpA2 TpB2
Transmitter & Receiver
PS0,PS1,PS2 BCLKON XRST (Power On Reset)
Control Unit
Transmitter & Receiver
PD
393.216MHz CLK PLL XI,XO
2
EPSON
Rev. 1.0
S1R72900F00A
4. PIN LAYOUT
TPBIAS1
TPBIAS0
TPA1_N
TPB1_N
TPA0_N
TPB0_N 34
TPA1_P
TPB1_P
TPA0_P
TPB0_P 35
AVDD
AVSS
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
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AVSS AVSS AVDD AVDD XRST FC0 FC1 PVDD PVSS
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
33
AVSS
R1
R0
32 31 30 29 28 27 26 25 SPC7290F0A 24 23 22 21 20 19 18 17
AVSS AVDD AVDD TEST1 TEST0 XTEST_MODE VDD VDD CPS DIRECT PS0 PS1 PS2 BCLKON VSS VSS
OSCVSS XI XO OSCVDD VDD VSS VSS
LREQ
SCLK
BNC
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
LPS
Rev. 1.0
EPSON
VDD
3
S1R72900F00A
5. PIN ASSIGNMENT TABLE
The items listed on the pin assignment table are as follows:
PIN No. PIN NAME POWER PLANE
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I/O ATTR
DRIVE TERM
Pin number Pin name of the SIR72900F00A Supply voltage for each I/O cell 3.3-V power supply for the digital circuit VDD : 3.3-V power supply for the analog circuit AVDD : 3.3-V power supply for the PLL circuit PVDD : OSCVDD : 3.3-V power supply for the oscillating circuit Type of I/O cells I : Input pin O : Output pin I/O : Input/output pin P : Power pin Drivability of output pins Resistance of the pull-up or pull-down resistor provided on the pin
4
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Rev. 1.0
S1R72900F00A
POWER PLANE VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AVDD AVDD AVSS AVSS AVDD AVDD AVDD AVDD AVDD AVSS AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVSS I/O ATTR I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I - - - I/O I I I I I - - I I I - - - - I/O I/O I/O I/O O - O O - I/O I/O I/O I/O O - DRIVE(mA) 3.3V IOL IOH - - -6 6 -2 2 -6 6 -6 6 -6 6 -6 6 -6 6 -6 6 -6 6 -6 6 -6 6 -6 6 - - - - - - - - - - -6 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TERM() 3.3V - - - - - - - - - - - - - - - - - -
-
PIN No. 1 2 3 4 5 6 7 8 Sh 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
PIN NAME LREQ SCLK BNC CTL0 CTL1 D0 D1 D2 et4U.com D3 D4 D5 D6 D7 PD LPS VDD VSS VSS BCLKON PS2 PS1 PS0 DIRECT CPS VDD VDD XTEST_MODE TEST0 TEST1 AVDD AVDD AVSS AVSS TPB0_N TPB0_P TPA0_N TPA0_P TPBIAS0 AVSS R0 R1 AVDD TPB1_N TPB1_P TPA1_N TPA1_P TPBIAS1 AVSS
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Rev. 1.0
EPSON
5
S1R72900F00A
POWER PLANE AVSS AVSS AVDD AVDD VDD PVDD PVDD PVDD PVSS OSCVSS OSCVDD OSCVDD OSCVDD VDD VSS VSS I/O ATTR - - - - I - - - - - I O - - - - DRIVE(mA) 3.3V IOL IOH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TERM() 3.3V - - - - 100 - - - - - - - - - - -
PIN No. 49 50 51 52 53 54 55 56 S 57 h 58 59 60 61 62 63 64
PIN NAME AVSS AVSS AVDD AVDD XRST FC0 FC1 PVDD et4U.c PVSS OSCVSS XI XO OSCVDD VDD VSS VSS
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S1R72900F00A
6. PIN DESCRIPTION
Pin name AVDD AVSS PVDD PVSS VDD VSS OSCVDD OSCVSS www..com TPA0_P TPA0_N TPB0_P TPB0_N TPBIAS0 TPA1_P TPA1_N TPB1_P TPB1_N TPBIAS1 R1, R0 Function Pin No. Analog circuit power supply pin 30,31,42,51,52 Analog circuit ground pin 32,33,39,48,49,50 PLL circuit power supply pin 56 PLL circuit ground pin 57 Digital circuit power supply pin 16,25,26,62 Digital circuit ground pin 17,18,63,64 Oscillating circuit power supply pin 61 Oscillating circuit ground pin 58 Port 0, TPA+ I/O signal 37 Port 0, TPA- I/O signal 36 Port 0, TPB+ I/O signal 35 Port 0, TPB- I/O signal 34 Port 0, TP bias voltage supply pin 38 Port 1, TPA+ I/O signal 46 Port 1, TPA- I/O signal 45 Port 1, TPB+ I/O signal 44 Port 1, TPB- I/O signal 43 Port 1, TP bias voltage supply pin 47 Connect 6.0k(1.0%) between the external reference resistor connecting 41,40 pins R1 and R0. Power down input pin 14 Connect this pin to VSS during normal operation. Bus Manager Contender/Link-On pin The status of this pin determines whether 19 the bus manager function is used at the time of hard reset. See 7.4.3. Request signal from the Link layer 1 controller IC PHY/LINK interface bidirectional control signal 4,5 6,7,8,9, PHY/LINK interface bidirectional data signal 10,11,12,13 49.152 MHz system clock to the Link 2 layer controller IC Link power status pin. A signal used to monitor whether the Link 15 layer controller IC is active. Power status pin These pins configure the POWER CLASS bit of the Self-ID packet. PS0, 20,21,22 PS1, and PS2 are respectively bits 21, 22, 23 of the Self-ID packet. Configured according to the isolation barrier configuration between PHY and LINK. 23 Connect this pin to VDD for DC or single capacitor AC connection. Pin typ. Supply Supply Supply Supply Supply Supply Supply Supply Differential Differential Differential Differential Supply Differential Differential Differential Differential Supply Analog I/O - - - - - - - - I/O I/O I/O I/O O I/O I/O I/O I/O O O
PD
Hysteresis
I
BCLKON
CMOS
I/O
LREQ CTL0, CTL1 D0 to D7 SCLK LPS
Hysteresis Hysteresis Hysteresis
I I/O I/O O
Hysteresis
I
PS2 PS1 PS0
CMOS
I
DIRECT
CMOS
I
Rev. 1.0
EPSON
7
S1R72900F00A
Pin name XTEST_MODE Function Test pin Connect this pin to VDD during normal operation. Reset pin The SIR72900F00A is initialized when this pin is set to 0. After turning on the power supply, for at least 2ms, maintain XRST = 0. Set this pin to 1 during normal operation. Cable Power Status detection pin Connect this pin to the cable power through a 240k resistor. Also, connect a diode (VF = 0.4V) between the PHY-VDD. Signal indicating the cable status. Outputs HIGH when all the ports do not receive bias voltage from the node on the other side. Connection pin for PLL filter The SIR72900F00A does not need external capacitor. Set this pin to open. Connection pin for PLL filter The SIR72900F00A does not need external capacitor. Set this pin to open. Pin for a 24.576MHz crystal oscillator Pin for a 24.576MHz crystal oscillator Test pin Connect this pin to VSS during normal operation. Test pin Connect this pin to VSS during normal operation. Pin No. 27 Pin typ. CMOS I/O I
XRST
53
Hysteresis
I
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CPS
Hysteresis
I
BNC
3
CMOS
O
FC0
54
Analog
O
FC1 XI XO TEST0
55 59 60 28
Analog
O
CMOS
I
TEST1
29
CMOS
I
8
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Rev. 1.0
S1R72900F00A
7. FUNCTIONAL DESCRIPTION
7.1 Control Register
7.1.1 Accessing the register The registers on the SIR72900F00A are accessed from the Link layer controller IC. For details, see Section 7.4.4 Link interface. Table 7.1 Registers Name Register0 Register1 Register2 www..com Register3 Register4 Register5 Register6 Register7 - - - - - - - - Address 0 1 2 3 4 5 6 7 0000 Physical_ID R PS 0001 RHB IBR Gap_count 0010 Extended Total_ports 0011 Max_speed Delay 0100 LCtrl Contender Jitter Power_class 0101 Watchdog ISBR Loop Pwr_fail Timeout Port_event Enab_accel Enab_multi 0110 0111 Page_Select Port_Select 1000 Register8 1001 Register9 1010 RegisterA 1011 RegisterB 1100 RegisterC 1101 RegisterD 1110 RegisterE 1111 RegisterF
7.1.2 Register bits This section explains the control register bits of the SIR72900F00A. In the R/W column, R means read only and R/W means readable/writable. The Power Reset Value column shows the initial value (0 or 1) which each bit takes after power-on reset. 7.1.2.1 Register 0 Address 0x01 Bit Symbol 0: RHB 1: IBR 2: Gap_count [0] 3: Gap_count [1] 4: Gap_count [2] 5: Gap_count [3] 6: Gap_count [4] 7: Gap_count [5] R/W R/W R/W R/W R/W R/W R/W R/W R/W Power Reset Value 0 0 1 1 1 1 1 1 Description Root Hold Bit Initiate Bus Reset Gap Count_bit0 Gap Count_bit1 Gap Count_bit2 Gap Count_bit3 Gap Count_bit4 Gap Count_bit5
Bits 0 to 5: Physical Node ID This register address 00h is output as a status to the PHY/LINK interface after transmission of a Self-ID packet. These bits indicate Node IDs that were determined during a Self-ID period and they are determined when transmitting a SelfID packet during a Self-ID period. These bits are initialized by bus reset (BR). Bit 6: Root Indicator This bit is determined during a Tree-ID period and it indicates the root setting for its node. When this bit is '1', this node is set as the root and initialized by bus reset. Bit 7: Cable Power Status This bit indicates the cable power supply status reflecting the status of the CPS pin. When this bit is '1', it indicates that the power is supplied through the cable. Rev. 1.0
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S1R72900F00A
7.1.2.2 Register 1 Address 0x01 Bit Symbol 0: RHB 1: IBR 2: Gap_count [0] 3: Gap_count [1] 4: Gap_count [2] 5: Gap_count [3] 6: Gap_count [4]
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R/W R/W R/W R/W R/W R/W R/W R/W R/W
Power Reset Value 0 0 1 1 1 1 1 1
Description Root Hold Bit Initiate Bus Reset Gap Count_bit0 Gap Count_bit1 Gap Count_bit2 Gap Count_bit3 Gap Count_bit4 Gap Count_bit5
7: Gap_count [5]
Bit 0: Root Hold Bit This bit is set automatically by PHY configuration packet transmission. When this bit is '1', it is a request that the node should be the root at the next bus reset. Bit 1: Initiate Bus Reset Setting this bit immediately issues a bus reset command. When this bit is '1', a bus reset is issued. This bit is initialized by bus reset. Bits 2 to 7: Gap Count These bits are also set automatically by PHY Configuration packet transmission indicating Gap Count values. They retain the value at the first bus reset after configuration, and are initialized at the second bus reset. 7.1.2.3 Register 2 Address 0x03 Bit Symbol 0: Max_speed [0] 1: Max_speed [1] 2: Max_speed [2] 3: Reserved 4: Delay [0] 5: Delay [1] 6: Delay [2] 7: Delay [3] R/W R R R R R R R R Power Reset Value 0 1 0 0 0 0 1 0 Delay Delay Delay Delay Speed Speed Speed Description
Bits 0 to 2: Extended register The register map that the SIR72900F00A supports. '111b' is read. Bits 3 to 7: Total of Port The number of ports on the SIR72900F00A. Normally, 2 ('00010b') is read. 7.1.2.4 Register 3 Address 0x04 Bit Symbol 0: LCtrl 1: Contender 2: Jitter [0] 3: Jitter [1] 4: Jitter [2] 5: Power_class [0] 6: Power_class [1] 7: Power_class [2] 10 R/W R/W R/W R R R R/W R/W R/W Power Reset Value 1 See discription 0 0 0 0 0 0 Description Link Control Contender Jitter Jitter Jitter Power Class Power Class Power Class Rev. 1.0
EPSON
S1R72900F00A
Bits 0 to 2: Speed The maximum transmission speed the SIR72900F00A supports. Normally, 2 ('010b') is read. Bit 3: Reserved Bits 4 to 7: Delay The SIR72900F00A's repeat delay in the worst cases. Normally, 2 ('0010b') is read. The maximum repeat delay time of the SIR72900F00A is 0.184 s. 7.1.2.5 Register 4 Address 0x04 Bit Symbol 0: LCtrl 1: Contender 2: Jitter [0] 3: Jitter [1] 4: Jitter [2] 5: Power_class [0] 6: Power_class [1] 7: Power_class [2] R/W R/W R/W R R R R/W R/W R/W Power Reset Value 1 See discription 0 0 0 0 0 0 Description Link Control Contender Jitter Jitter Jitter Power Class Power Class Power Class
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Bit 0: Link Control This bit controls the value of the L (link_active) field of the Self-ID packet. The L (link_active) field of the Self-ID packet reflects the logical multiplication between this bit and LPS signal. This bit is initialized to '1' as bus reset occurs. Bit 1: Contender This bit reflects the c (CONTENDER) field of the Self-ID packet. This bit has the same meaning as the c (CONTENDER) field of the Self-ID packet. This bit reflects the value of the BCLKON pin when hardware reset occurs. Bits 2 to 4: Jitter A difference between the maximum and minimum repeat delays of the SIR72900F00A. Normally, 0'000b' is read. The repeat jitter of the SIR72900F00A is 20 ns. Bits 5 to 7: Power Class These bits reflect the pwr (POWER_CLASS) field of the Self-ID packet. They have the same meaning as the pwr (POWER_CLASS) field of the Self-ID packet. These bits are initialized to the value of pins PS0, PS1, and PS2 when hardware reset occurs. The relationships between the bits and pins PS0, PS1, and PS2 are as follows: bit5:PS0(Pin22) bit6:PS1(Pin21) bit7:PS2(Pin20)
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S1R72900F00A
7.1.2.6 Register 5 Address 0x05 Bit Symbol 0: Watchdog 1: ISBR 2: Loop 3: Pwr_fail 4: Timeout 5: Port_event 6: Enab_accel
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R/W R/W R/W R/W R/W R/W R/W R/W R/W
Power Reset Value 0 0 0 1 0 0 0 0
Description Watchdog Initiate Short Bus Reset Loop detect Cable power failure detect Arbtration state machine timeout Port_event detect Enable arbitration acceleration Enable multi-speed packet concatenation
7: Enab_multi
Bit 0: Watchdog When set to '1,' this bit communicates the status of Loop, Power_fail, and Arb_timeout to the Link layer controller IC, regardless of the status of the PHY/LINK interface. When a resume action starts on any port, this bit sends a resume interrupt signal regardless of the value of Int_enable. Bit 1: Initiate Short (Arbitrated) Bus Reset Setting this bit to '1' issues short bus reset. This bit is cleared when the short bus reset completes. Bit 2: Loop detect When this bit is '1,' the bus is looped. This bit is cleared when hardware reset occurs or '1' is written. Bit 3: Cable power failure detect When this bit is '1,' it means that the PC bit has changed from 1 to 0. This bit is cleared when '1' is written. Bit 4: Arbitration state machine timeout When this bit is '1,' it means that the node had been in a state other than Tree_IDStart longer than MAX_ARB_STATE_TIME. This bit is cleared when hardware reset occurs or '1' is written. Bit 5: Port_event detect When Int_enable is '1,' detection of a change in the Connected, Bias, Disabled, or Fault bit sets this bit to '1.'Also, when Watchdog is '1,' a Resume process sets this bit to '1.' This bit is cleared when hardware reset occurs or '1' is written. Bit 6: Enable arbitration acceleration Setting this bit to '1' causes Ack-acceleration arbitration and fly-by arbitration. When this bit is set to '0,' no acceleration arbitration occurs. This bit is initialized as hardware reset occurs. Bit 7: Enable multi-speed packet concatenation When this bit is set to '1,' a joint packet transmission request requires a speed code. When this bit is set to '0,' joint packet transmission is done at the same speed as the first packet transmission. This bit is initialized as hardware reset occurs.
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7.1.2.7 Register 6 Address 0x06 Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description
7: Reserved
Bits 0 to 7: Reserved 7.1.2.8 Register 7 Address 0x07 Bit Symbol 0: Page_select [0] 1: Page_select [1] 2: Page_select [2] 3: Reserved 4: Port_select [0] 5: Port_select [1] 6: Port_select [2] 7: Port_select [3] R/W R/W R/W R/W R R/W R/W R/W R/W Power Reset Value 0 0 0 0 0 0 0 0 Description
Bits 0 to 2: Page Select These bits specify what page between 1000b and 1111b of the PHY register should be accessed. Bit 3: Reserved Bits 4 to 7: Port Select When the Page_select bit selects Port Status Page, these bits specify what port between 1000b and 1111b of the PHY register should be accessed.
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Table 7.2 Registers of Page_Select 0 Name Register00 Register01 Register02 Register03 Register04 Register05 Register06 Register07
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Address 1000 1001 1010 1011 1100 1101 1110 1111
0
1 2 3 AStat BStat Negotiated_speed Int_enable
4 Child Fault
5 Connected
6 Bias
7 Disabled
7.1.3 Page_select 0 bits 7.1.3.1 Register 00 Address 0x08 Bit Symbol 0: Astat [0] 1: Astat [1] 2: Bstat [0] 3: Bstat [1] 4: Child 5: Connected 6: Bias 7: Disabled R/W R R R R R R R R/W Power Reset Value 0 0 0 0 0 0 0 See description Description Status of TPA Status of TPA Status of TPB Status of TPB Child Connected Cable Bias Port Disabled
Bits 0 to 1: Status of TPA These bits indicate the status of TPA. The meaning of these bits is as follows: '11b':Z '01b':1 '10b':0 '00b':invalid Bits 2 to 3: Status of TPB These bits indicate the status of TPB. The meaning of these bits is as follows: '11b':Z '01b':1 '10b':0 '00b':invalid Bit 4: Child When this bit is '1,' the port is a Child. When this bit is '0,' the port is a Parent. This bit is initialized by bus reset, and determined during a Tree-ID period. Bit 5: Connected When this bit is '1,' it indicates that the port recognizes a node is connected. Bit 6: Cable Bias This bit reflects the cable bias detected at the port. When this bit is '1,' it indicates that TpBias is detected at the port. Bit 7: Port Disabled When this bit is set to '1,' the port is disabled. This bit is initialized as hardware reset occurs. 14
EPSON
Rev. 1.0
S1R72900F00A
7.1.3.2 Register 01 Address 0x09 Bit Symbol 0: Negotiated_speed [0] 1: Negotiated_speed [1] 2: Negotiated_speed [2] 3: Int_enable 4: Fault 5: Reserved 6: Reserved
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R/W R R R R/W R/W R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description Negotiated speed Negotiated speed Negotiated speed Enable port event interrupt fault
7: Reserved
Bits 0 to 2: Negotiated speed These bits indicate the speed of the node connected to the port. They are initialized by bus reset, and determined during a Self-ID period. The meaning of these bits is as follows: '000b': The maximum transmission speed is 100 Mbps. '001b': The maximum transmission speed is 200 Mbps. '010b': The maximum transmission speed is 400 Mbps. Bit 3: Enable port event interrupt When this bit is set to '1,' the Port_event bit is set to '1' when a change in the Connected, Bias, Disabled, or Fault bit occurs. This bit is initialized as hardware reset occurs. Bit 4: Fault When this bit is '1,' it indicates that an error has occurred during suspend/resume operation. This bit is cleared when hardware reset occurs or '1' is written. Bits 5 to 7: Reserved 7.1.3.3 Register 02 Address 0x0A Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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7.1.3.4 Register 03 Address 0x0B Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description
7: Reserved
Bits 0 to 7: Reserved
7.1.3.5 Register 04 Address 0x0C Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
7.1.3.6 Register 05 Address 0x0D Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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S1R72900F00A
7.1.3.7 Register 06 Address 0x0E Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description
7: Reserved Bits 0 to 7: Reserved
7.1.3.8 Register 07 Address 0x0F Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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S1R72900F00A
Table 7.3 Registers of Page_Select 1 Name Register10 Register11 Register12 Register13 Register14 Register15 Register16 Register17
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Address 1000 1001 1010 1011 1100 1101 1110 1111
0
1
2
3 4 Complience_level Vendor_ID [16:23] Vendor_ID [8:15] Vendor_ID [0:7] Product_ID [16:23] Product_ID [8:15] Product_ID [0:7]
5
6
7
7.1.4 Page_select 1 bits 7.1.4.1 Register 10 Address 0x08 Bit Symbol 0: Compliance_level [0] 1: Compliance_level [1] 2: Compliance_level [2] 3: Compliance_level [3] 4: Compliance_level [4] 5: Compliance_level [5] 6: Compliance_level [6] 7: Compliance_level [7] R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 1 Description Compliance_level Compliance_level Compliance_level Compliance_level Compliance_level Compliance_level Compliance_level Compliance_level
Bits 0 to 7: Compliance Level Normally, 1 ('01h') for P1394a-compliant is read. 7.1.4.2 Register 11 Address 0x09 Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
18
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7.1.4.3 Register 12 Address 0x0A Bit Symbol 0: Vendor_ID [16] 1: Vendor_ID [17] 2: Vendor_ID [18] 3: Vendor_ID [19] 4: Vendor_ID [20] 5: Vendor_ID [21] 6: Vendor_ID [22]
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description Vendor_ID_bit16 Vendor_ID_bit17 Vendor_ID_bit18 Vendor_ID_bit19 Vendor_ID_bit20 Vendor_ID_bit21 Vendor_ID_bit22 Vendor_ID_bit23
7: Vendor_ID [23]
Bits 0 to 7: Vendor ID [16:23] For the SIR72900F00A, '00h' is read.
7.1.4.4 Register 13 Address 0x0B Bit Symbol 0: Vendor_ID [8] 1: Vendor_ID [9] 2: Vendor_ID [10] 3: Vendor_ID [11] 4: Vendor_ID [12] 5: Vendor_ID [13] 6: Vendor_ID [14] 7: Vendor_ID [15] Bits 0 to 7: Vendor ID [8:15] For the SIR72900F00A, '00h' is read. R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description Vendor_ID_bit8 Vendor_ID_bit9 Vendor_ID_bit10 Vendor_ID_bit11 Vendor_ID_bit12 Vendor_ID_bit13 Vendor_ID_bit14 Vendor_ID_bit15
7.1.4.5 Register 14 Address 0x0C Bit Symbol 0: Vendor_ID [0] 1: Vendor_ID [1] 2: Vendor_ID [2] 3: Vendor_ID [3] 4: Vendor_ID [4] 5: Vendor_ID [5] 6: Vendor_ID [6] 7: Vendor_ID [7] Bits 0 to 7: Vendor ID [0:7] For the SIR72900F00A, '48h' is read. R/W R R R R R R R R Power Reset Value 0 1 0 0 1 0 0 0 Description Vendor_ID_bit0 Vendor_ID_bit1 Vendor_ID_bit2 Vendor_ID_bit3 Vendor_ID_bit4 Vendor_ID_bit5 Vendor_ID_bit6 Vendor_ID_bit7
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7.1.4.6 Register 15 Address 0x0D Bit Symbol 0: Product_ID [16] 1: Product_ID [17] 2: Product_ID [18] 3: Product_ID [19] 4: Product_ID [20] 5: Product_ID [21] 6: Product_ID [22]
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description Product_ID_bit16 Product_ID_bit17 Product_ID_bit18 Product_ID_bit19 Product_ID_bit20 Product_ID_bit21 Product_ID_bit22 Product_ID_bit23
7: Product_ID [23]
Bits 0 to 7: Product ID [16:23] For the SIR72900F00A, '00h' is read.
7.1.4.7 Register 16 Address 0x0E Bit Symbol 0: Product_ID [8] 1: Product_ID [9] 2: Product_ID [10] 3: Product_ID [11] 4: Product_ID [12] 5: Product_ID [13] 6: Product_ID [14] 7: Product_ID [15] Bits 0 to 7: Product ID [8:15] For the SIR72900F00A, '02h' is read. R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 1 0 Description Product_ID_bit8 Product_ID_bit9 Product_ID_bit10 Product_ID_bit11 Product_ID_bit12 Product_ID_bit13 Product_ID_bit14 Product_ID_bit15
7.1.4.8 Register 17 Address 0x0F Bit Symbol 0: Product_ID [0] 1: Product_ID [1] 2: Product_ID [2] 3: Product_ID [3] 4: Product_ID [4] 5: Product_ID [5] 6: Product_ID [6] 7: Product_ID [7] Bits 0 to 7: Product ID [0:7] For the SIR72900F00A, '01h' is read. R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 1 Description Product_ID_bit0 Product_ID_bit1 Product_ID_bit2 Product_ID_bit3 Product_ID_bit4 Product_ID_bit5 Product_ID_bit6 Product_ID_bit7
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Table 7.3 Registers of Page_Select 1 Name Register70 Register71 Register72 Register73 Register74 Register75 Register76 Register77
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Address 1000 1001 1010 1011 1100 1101 1110 1111
0
1
2
3
4
5
6 7 RemSCLk HostIsbr
7.1.5 Page_select 7 bits 7.1.5.1 Register 70 Address 0x08 Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: RemSCLK 7: HostIsbr R/W R R R R R R R/W R/W Power Reset Value 0 0 0 0 0 0 0 0 Remain SCLK Host Isbr Description
Bits 0 to 5: Reserved Bit 6: Remain SCLK When this bit is set to '1,' SCLK output continues even if LPS is deasserted. When this bit is '0,' the IC operates as per IEEE 1394a-2000. Bit 7: Host Isbr When this bit is '1,' the SIR72900F00A issues short bus reset when LPS is deasserted. When this bit is '0,' the IC operates as per IEEE 1394a-2000.
7.1.5.2 Register 71 Address 0x09 Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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7.1.5.3 Register 72 Address 0x0A Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description
7: Reserved
Bits 0 to 7: Reserved
7.1.5.4 Register 73 Address 0x0B Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
7.1.5.5 Register 74 Address 0x0C Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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7.1.5.6 Register 75 Address 0x0D Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved
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R/W R R R R R R R R
Power Reset Value 0 0 0 0 0 0 0 0
Description
7: Reserved
Bits 0 to 7: Reserved
7.1.5.7 Register 76 Address 0x0E Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
7.1.5.8 Register 77 Address 0x0F Bit Symbol 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits 0 to 7: Reserved R/W R R R R R R R R Power Reset Value 0 0 0 0 0 0 0 0 Description
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S1R72900F00A 7.2 Data Format
7.2.1 Self-ID packet The Self-ID packets the SIR72900F00A transmits are 2-quadlet packets in the format shown in Figure 7.1. The SIR72900F00A transmits the following Self-ID packet during Self-ID period of bus initialization. The SIR72900F00A also transmits a Self-ID packet automatically as a response to a Ping packet.
0 # 1 2 3 4 5 6 7 8 0 9 L # # # # # # # # sp # # # c # # pwr # # # # # p1 # 0 # # i # m
phy-ID
gap_cnt
rsv
p0
logical inverse of first quadlet
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Figure 7.1 Self-ID packet format phy_ID: physical_ID field Reflects the ID node of the IC. L: LPS, LCtrl field Reflects the logical multiplication of the LPS pin and the LCtrl bit of PHY Register 4 at the time of Self-ID packet transmission.
gap_cnt: gap_cnt field Reflects the value of Gap_Count of PHY Register 1. sp: PHY_SPEED field 00 = 98.304 Mbps (S100) 01 = 98.304/196.608 Mbps (S100/S200) 10 = 98.304/196.608/393.216 Mbps (S100/S200/S300) 11 = Reserved Applicable speeds are stored. For the SIR72900F00A, this field is fixed to '10b.' rsv: C: pwr: Fixed to '00b.' CONTENDER field Reflects the value of the Contender bit of PHY Register 4. POWER_CLASS field bit21 = PS0(Pin22) bit22 = PS1(Pin21) bit23 = PS2(Pin20) Reflects the Pwr bit of PHY Register 4. The IEEE P1394a-2000 standards define this field as follows: 000 = The node does not need a power supply. The node does not repeat the power supply. 001 = The node has its own power supply and is able to supply a minimum of 15 W. 010 = The node has its own power supply and is able to supply a minimum of 30 W. 011 = The node has its own power supply and is able to supply a minimum of 45 W. 100 = The node can consume power up to 3 W from the cable. However, it does not consume any power to enable the Link or upper layers. 101 = Reserved 110 = The node can consume power up to 3 W from the cable. It can consume more power up to 3 W to enable the Link or upper layers. 111 = The node can consume power up to 3 W from the cable. It can consume more power up to 7 W to enable the Link or upper layers.
p0, p1: Port connection status field Indicates the port status. 11 = The port is active and connected to a child node. 10 = The port is active and connected to a parent node. 01 = The port is inactive (disabled, disconnected, or suspended). 24
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I: m: initiated_reset field Indicates that the node has issued BusReset. more_packets field This field is set to '1' when more than one Self-ID packet is sent. However, for the SIR72900F00A, this field is fixed to '0.'
7.2.2 Link-on Packet
01
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phy-ID
0000
0000
0000
0000
0000
0000
logical inverse of first quadlet
Figure 7.2 Link-on packet format
7.2.3 PHY Configuration Packet
00 root-ID RT gap_cnt 0000 0000 0000 0000
logical inverse of first quadlet
Figure 7.3 PHY Configuration packet format
7.2.4 Extended PHY Packet 7.2.4.1 Ping Packet
00 phy-ID 00 type(0) 00 0000 0000 0000 0000
logical inverse of first quadlet
Figure 7.4 Ping packet format
7.2.4.2 Remote Access Packet
00 phy-ID 00 type(1/5h) page port reg reserved
logical inverse of first quadlet
Figure 7.5 Remote Access packet format
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7.2.4.3 Remote Reply Packet
00 phy-ID 00 type(3/7h) page port reg data
logical inverse of first quadlet
Figure 7.6 Remote Reply packet format
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00
Remote Command Packet
phy-ID 00 type(8h) 000 port 0000 data
logical inverse of first quadlet
Figure 7.7 Remote Command packet format
7.2.4.5 Remote Confirmation Packet
00 phy-ID 00 type(Ah) 000 port 0000 f c b d ok cmnd
logical inverse of first quadlet
Figure 7.8 Remote Confirmation packet format
7.2.4.6 Resume Packet
00 phy-ID 00 type(Fh) 00 0000 0000 0000
logical inverse of first quadlet
Figure 7.9 Resume packet format
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S1R72900F00A 7.3 Cable Port Interface
7.3.1 Cable port interface circuit Figure 7.10 shows a circuit diagram of the cable port interface.
PHYVDD CPS VF=0.4V 1F TPBIAS
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240k CABLE POWER
56 TPA P TPA N
56 TWIST PAIR A
CABLE PORT TPB P TPB N 56 240pF 56 5.1k OUTER SHIELD TERMINATION TWIST PAIR B
Figure 7.10 Cable port interface circuit
Figure 7.11 shows an example of outer shield circuit of the cable port.
OUTER CABLE SHIELD
1M
0.01F
0.01F
Figure 7.11 Cable port outer shield circuit
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S1R72900F00A
Cables specifically designed as per IEEE 1394 are used as media for the cable port interface. Data is transmitted through two shielded pairs of twisted cables. As shown in Figure 7.10, each twisted pair cable is connected to the TpB pair of the node to which the TpA pair of the own node. Both TpA and TpB require two 56 terminating resistors appropriate to the cable impedance. Locate these terminating resistors as close to the IC pin as possible. On the TpA side, TpBias is connected to the terminating resistor intermediate node to set inphase DC potential of the cable. To TpBias, connect a 1-F capacitor for decoupling. On the TpB side, connect a 5.1k resistor and a 240-pF capacitor to the terminating resistor intermediate node for pulldown. The 240-pF capacitor is for decoupling. Connect the CPS pin to the cable power through a 240k resistor.
www..com 7.3.2 Port
state The SIR72900F00A complies with the IEEE 1394a-2000 standards. The IEEE P1394a-2000 standards define the following five port states. -Disabled: A 'disabled' port does not output signals to TpBias and TpA/TpB. And the port in this state does not detect signals input to Bias and TpA/TpB. When the connection detection circuit detects a change in cable connection, this port outputs an interrupt to the upper layer if the Int_enable bit is set. -Disconnected: A 'disconnected' port has no physical cable connection to PHY on a different node and thus does not output signals to TpBias and TpA/TpB. And the port in this state does not detect signals input to Bias and TpA/TpB. -Suspended: A 'suspended' port does have physical cable connection to PHY on a different node but does not output signals to TpBias and TpA/TpB. And the port in this state does not detect signals input to TpA/TpB. On this port, only the bias detection and connection detection circuits are in operation. -Resuming: A 'resuming' port has physical cable connection to PHY on a different node and outputs signals to TpBias. On detection of bias, the port stays for a specified time and becomes active. During the resuming period, it does not detect signals input to TpA/TpB. -Active: An 'active' port has physical cable connection to PHY on a different node and outputs signals to TpBias and TpA/ TpB. The port in this state detects signals input to Bias and TpA/TpB.
7.3.3 Connection detecting circuit The SIR72900F00A is equipped with a built-in connection detecting circuit. Connection detecting circuit is a circuit to detect the connected state of the cables and is effective while the port is not outputting TpBias.
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7.3.4 Suspend/Resume There are two operations for the port state to transit from Active to Suspend state. When receiving TX SUSPEND that was output by Suspend Initiator (RX SUSPEND) The port (the Suspend Target) that received the RX SUSPEND enters the Suspend state. The node also outputs TX SUSPEND into Active ports other than the port that received RX SUSPEND, and the port is set as the Suspend Initiator. The Suspend Initiator port then also enters the Suspend state. TX SUSPEND is transmitted until the position of this leaf node to set at the Suspend state. However, if the IEEE13941995 node, the Disabled port and the Suspend port are present on its way, TX SUSPEND will be transmitted to stop at their positions. Even when the port is set at Suspend state, the Fault bit is set to indicate that the Suspend state is not set normally when the Bias of the connection partner node was detected. The conditions under which the port of the Suspend state starts the Resume operation to enter the Active state are as follows. www..com -The Bias of the connection partner node is detected and the Fault bit is cleared. -The Resume packet is received. -The Remote Command packet, which the Resume bits for the port were set to, is received. If the Boundary node is not set, the other Suspended ports except this node will also start Resume operation simultaneously when the ports in the Suspend or Disconnected state start Resume operation with the Bias detected (other than Resume packet and Remote Command packet). The Resume operation outputs TPBIAS, and it is terminated normally when the Bias of the connection partner node is detected. It then enters the Active state. However, it returns to the Suspended state to set the Fault bit, indicating that Resume operation was terminated normally if the Bias from the connection partner node cannot be detected. When receiving the Resume Command packet which the Suspend bit for its own port was set to The Remote Command packet is transferred two ways, from nodes other than its own node, and from the Link layer controller IC, which correspondent to the upper level layer of its own node. Either way, the Remote Confirmation packet is transferred to all ports and the PHY/LINK interface when the S1R72900F00A receives the Remote Command packet. Bus reset is then issued to all ports other than the port (Suspend Initiator) that the Suspend bit is set to, and the node enters the reset state. Simultaneously, the port which the Suspend bit is set to outputs TX SUSPEND and it then enters the Suspend state.
7.3.5 Processing Unused Ports If there are ports to be not used out of two SiR72009F00A cable ports, the pin should be processed as shown Figure 712.
TPBIAS TPA P TPA N 1F TPB P TPB N
GND
Figure 7.12 Processing Unused Ports
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S1R72900F00A 7.4 Link Layer Controller Interface
7.4.1 Connection The SIR72900F00A can connect to a Link layer controller IC regardless of the existence of an isolation barrier. For DC connection, connect the DIRECT pin to VDD as shown in Figure 7.13.
SCLK LREQ D[0:7]
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CTL[0:1] Link LPS LINKON PHY S1R72900
VDD DIRECT
Figure 7.13 SIR72900F00A -to-Link chip connection diagram (DC connection)
The SIR72900F00A has a bus holder circuit on the interface pin for the Link layer controller IC. This enables AC connection as shown in Figure 7.14. For AC connection (with a single capacitor), also connect the DIRECT pin to VDD.
SCLK LREQ D[0:7] CTL[0:1] Link LPS LINKON VDD PHY S1R72900
DIRECT
Figure 7.14 SIR72900F00A -to-Link chip connection diagram (AC connection)
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As shown in Figure 7.15, use a 1000-pF coupling capacitor for AC connection. * The SIR72900F00A is not in support of the IEEE1394 specification Annex J isolation barrier.
Bus Holder
Bus Holder
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C=1000pF
Figure 7.15 AC coupling connection
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7.4.2 LPS (Link Power Status) By inputting to the LPS pin, the S1R72900F00A is set to enable/disable the PHY/LINK interface. If the S1R72900F00A detects LPS = LOW during a TLPS RESET period, the PHY/LINK interface is set to the disable state to output LOW to the SCLK, CTL0-1 and D0-7. (While LOW is set when the PHY/LINK interface is DC connection, "Hi-Z" is set when it is AC connection.) However, if Page select7 Register 70 bit 6 was set, SCLK is not terminated and continues to output a clock signal even when the PHY/LINK interface is set to disable. If the PHY/LINK interface was reset, all bus requests and register read requests are cancelled. Also, the S1R72900F00A recognizes that the packet transfer was terminated and operates, if the Link layer controller IC reset the PHY/LINK interface during packet transfer. When the PHY/LINK interface is set to disable period, the status output is not operated, therefore, this information is not output even after the PHY/LINK interface is set to enabled. When the S1R72900F00A detects LPS = HIGH after the PHY/LINK interface was reset and set to disable, SCLK output www..com starts after the disable state. If the PHY/LINK interface uses the DC connection, the S1R72900F00A outputs LOW to the 7 SCLK cycles CTL, D after detecting LPS, and outputs Receive (CTL[0:1] = 10b, D[0.7]=ffh) for Data Prefix to the PHY/LINK interface at the 8th SCLK, returning to normal operation. For AC connection, the S1R72900F00A outputs LOW to the 1SCLK cycle period CTL,D within 1 to 6 SCLK cycles after detecting LPS, returning to normal operation. Other periods will become "Hi-Z". In this case, it continues to output Receive for Data Prefix to the PHY/LINK interface until packet receiving is terminated if its node is receiving a packet.
LPS
TLPSH
TLPSL
Figure 7.16 LPS waveforms in AC connection
Table 7.5 LPS timing Symbol TLPSL TLPSH TLPS_RESET TLPS_DISABLE Item LPS low time (pulses) LPS high time (pulses) The time required until the SIR72900F00A detects LPS = 0 and resets the PHY/LINK interface. The time required until the SIR72900F00A detects LPS = 0 and disables the PHY/LINK interface. Min. 0.09 0.09 1.2 25 Max. 1.0 1.0 2.75 30 Unit m m m m
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The S1R72900F00A issues short bus reset (SBR) against other nodes connected when detecting LPS = "1". This function makes cancellation possible by clearing Page select7Register 70 bit 7. A typical external circuit for the LPS pin is shown in Figures 7.17, 18 and 19.
LPS pin LPS control signal
10k
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Figure 7.17 A typical direct connection and LPS external circuit 1 (with external signal control)
System 5V power supply
22k
LPS pin
33k
Figure 7.18 A typical direct connection and LPS external circuit 2 (without external signal control) * The LPS control signal shown Figure 7.17 is required to be 0.8 V lower when the power supply on the upper layer compared to the Link layer is set to OFF. For example, if the LPS control signal is output from the Link layer controller IC, LPS output is required to be GND output when the Link layer controller IC power supply is set to OFF. (For VDD output, LPS = "0" may not be recognized because the VDD potential may not become 0.8V lower.) Also, even when the system's power supply is connected to the LPS pin as shown in Figure 7.18, it is required to be 0.8V lower when the power supply on the upper layer compared to the Link layer is set to OFF. When using a 3.3V power supply for the Link layer controller IC, pay attention to the LPS connection because the VDD potential may not become 0.8V lower when the power supply is set to OFF.
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PHY VDD
10k
LPS pin
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LPS control signal
10k
Figure 7.19 A typical AC connection and LPS external circuit
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7.4.3 LinkOn The SIR72900F00A recognizes that the Link layer controller IC is inactive when it recognizes that LPS is deasserted or the Link_Active bit of the PHY register is '0.' LinkOn normally outputs LOW. However, the SIR72900F00A outputs a LinkOn signal when it receives a LinkOn packet sent to the node while it recognizes that the Link layer controller IC is inactive. If the Loop, Pwr_fail, Timeout, or Port_event bit of the PHY register changes to '1' during this period, the IC outputs a LinkOn signal as an interrupt output. The LinkOn signal is output as long as the Link layer controller IC is inactive. When the Link layer controller IC becomes active, LOW is output as a LinkOn signal. LinkOn signals are AC signals with a frequency of 6.144 MHz and a duty of 50%.
7.4.4 Link www..com
interface (LREQ, CTL[0:1], D[0:7]) The PHY/LINK interface of the SIR72900F00A complies with the IEEE 1394a-2000 standards. The PHY/LINK interface operates in four ways, LREQ-triggered request and CTL-triggered status transmission, packet transmission, and packet reception. The CTL-triggered operation is first controlled by the PHY. Upon receiving a packet, the SIR72900F00A starts packet reception operation. Figures 7.6 and 7.7 show CTL statuses and their meanings.
Table 7.6 Operation in which the SIR72900F00A controls CTL CTL[0:1] 00b 01b 10b 11b Operation Idle Status Receive Grant Description Idle status. The CTL is doing no operation. (Default mode) Transmits status information. Transmits the received packet. Grants the Link the right to control the PHY/LINK interface for packet transmission.
After the above Grant operation when the Link layer controller IC is able to control the PHY/LINK bus, the Link interface enters the operation mode as shown in Table 7.7.
Table 7.7 Operation in which the Link layer controller IC controls CTL CTL[0:1] 00b 01b Operation Idle Hold Description Completes the packet transmission and frees the PHY/LINK interface. * Holds the PHY/LINK interface until the data on the packet to be transmitted is determined. * Requests concatenated packet transmission. Transmits data on the transmitted packet to the PHY. Reserved.
10b 11b
Transmit Reserved
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7.4.4.1 LREQ To request packet transmission, access to the PHY register, or acceleration control, the Link layer controller IC inputs a serial signal synchronized with SCLK to the LREQ pin. The serial signal contains information on the request type, speed of the packet to be transmitted, and read/write command. The length of the LREQ serial signal varies depending on the type of the request. It is 6 bits for acceleration control requests, 7 bits for bus requests, 9 bits for register read requests, and 17 bits for register write requests. The serial signal must contain '0' as a stop bit at the end.
LR0
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LR1
LR2
LR3
LR4
LRn-1
LRn LRn=LREQn
Figure 7.20 LREQ stream
A packet transmission request uses the 7-bit-long format as shown in Table 7.8.
Table 7.8 Request format Bit(s) 0 1 to 3 4 to 5 6 Typ. Start Bit Request Type Request Speed Stop Bit Description Represents the start of transmission. Always '1'. Represents the request type as shown in Figure 7.13. Represents the packet transmission speed. Represents the completion of transmission. Always '0'.
Table 7.9 Speed format LREQ[4:5] 00 01 10 11 Data Rate 100Mbps 200Mbps 400Mbps Reserved
A read PHY chip register request uses the 9-bit-long format as shown in Table 7.10. A write register request uses the 17-bit-long format as shown in Table 7.11. Table 7.10 Read register format Bit(s) 0 1 to 3 4 to7 8 Typ. Start Bit Request Type Address Stop Bit Description Represents the start of transmission. Always '1'. Represents the request type as shown in Figure 7.13. Represents the address of the PHY register to be transmitted. Represents the completion of transmission. Always '0'.
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Table 7.11 Write register format Bit(s) 0 1 to 3 4 to 7 8 to 15 16 Typ. Start Bit Request Type Address Data Stop Description Represents the start of transmission. Always '1'. Represents the request type as shown in Figure 7.13. Represents the address of the PHY register to which data is written. Represents the PHY register data to be written. Represents the completion of transmission. Always '0'.
An acceleration control request uses the 6-bit-long format as shown in Table 7.12.
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Table 7.12 Acceleration control format Bit(s) 0 1 to 3 4 5 Typ. Start Bit Request Type Accelerate Stop Bit Description Represents the start of transmission. Always '1'. Represents the request type as shown in Figure 7.13. When this bit is '0,' arbitration acceleration can be disabled. When this bit is '1,' arbitration acceleration can be enabled. Represents the completion of transmission. Always '0'.
Table 7.13 Request type LREQ[1:3] 000 001 010 011 100 101 110 111 Typ. ImmReq IsoReq PriReq FairReq RdReg WrReg AccCtrl Reserved Description Immediate request Isochronous request Priority request Fair request Read data from the configured register Write data in the configured register Represents that PHY arbitration acceleration is disabled/enabled. Reserved
With FairReq and PriReq, the Link layer controller IC must start issuing LREQ after at least 1 SCLK after CTL starts the Idle operation. When CTL starts the Receive operation during or after the Link layer controller IC's issuance of these requests, the SIR72900F00A cancels them. Therefore, the Link layer controller IC must issue these requests again next time CTL starts the Idle operation. However, when the Enab_accel bit of PHY Register 5 is set to '1,' acceleration arbitration (Ack-Acceleration arbitration and Fly-by arbitration) is enabled, and an Ack packet (8-bit-long packet) is to be received, these requests are not canceled if the Receive operation starts. The cycle master Link layer controller IC issues PriReq to transmit a cycle start packet. The Link layer controller IC issues IsoReq to transmit an isochronous packet. IsoReq must be issued during or within eight SCLK cycles of transmission of a cycle start packet or an isochronous packet, or during or within four SCLK cycles of reception of such packets. The SIR72900F00A clears IsoReq only when it wins arbitration and transmits Grant to the Link layer controller IC, it detects a subaction gap, or when a bus request occurs. To transmit an Ack packet, ImmReq is issued during or within four SCLK cycles of reception of a Link packet. To satisfy ACK_RESPONSE_TIME, the Link layer controller IC must issue ImmReq immediately as it confirms the destination_ID of the received packet to check that the packet is sent to the node. As soon as the SIR72900F00A receives the packet, it acquires a bus, and the Link layer controller IC returns Grant. If the Link layer controller IC detects a CRC error, it must cancel the request rather than send data in response to the Grant. (See 7.4.4.3 Transmit.) Rev. 1.0
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S1R72900F00A
As soon as the reception of a register write request completes, the SIR72900F00A changes the data at the address. On receiving a register read request, the SIR72900F00A outputs the data at the address to the Link layer controller IC as a status transmission. If the output is interrupted by packet reception/transmission, the SIR72900F00A repeats the status output from the first bit until the output completes. When the SIR72900F00A receives a bus request (FairReq, PriReq, IsoReq or ImmReq), it ignores the next bus request until the preceding request is canceled by packet reception, packet transmission, or subaction gap (for IsoReq and ImmReq only). When the SIR72900F00A receives the next register read request before the preceding register read request completes, the operation becomes indefinite. Any bus request is cleared by a bus reset. The SIR72900F00A automatically sets an Accelerating bit with IsoReq, enabling acceleration arbitration.
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7.4.4.2 Status output The SIR72900F00A outputs information shown in Table 7.14 as a status output to the PHY/LINK interface. The SIR72900F00A asserts '01b' to the CTL pin and outputs information to the D[0:1] pin. The CTL pin outputs '01b' while the status output continues. The SIR72900F00A usually outputs the first four bits (Arbitration Reset Gap, Subaction Gap, Bus Reset, and PHY interrupt) necessary for the Link state machine as a status output. However, when it receives a register read request from the Link layer controller IC, it outputs all status information as a return value. In addition, when the SIR72900F00A has sent its Self-ID packet during the Self-ID period (when its Physical_ID has been determined), it automatically outputs the PHY register information on address '00h' containing its Physical_ID to the Link layer controller IC. Status output may be interrupted by packet reception/transmission. When the status output is interrupted, the SIR72900F00A repeats the status output according to the following rules. -The information that has been output before the interrupt is cleared and status output is not repeated. -Status output starts with the S[0:1] bit and is done in the units of 4 bits/16 bits.
CTL[0:1]
00
01
01
01
01
01
00
00
D[0:1]
00
S[0:1]
S[2:3]
S[4:5]
S[6:7]
S[14:15]
00
00
Figure 7.21 Status
Table 7.14 Status format Bit(s) 0 1 2 3 4 to 7 8 to 15 Typ. Arbitration Reset Gap Subaction Gap Bus Reset PHY Interrupt Address Data Description Detects an Arbitration Reset Gap. Detects a Subaction Gap. Detects a Bus Reset. Requests the host for an interrupt. PHY register address to which the status is returned Status data
The SIR72900F00A outputs a status as PHY Interrupt in the following cases. -When it detects that the bus is looped. -When it detects that the cable voltage has dropped. -When the state machine of the SIR72900F00A has timed out. -When the Port_event bit has changed to '1'. 38
EPSON
Rev. 1.0
S1R72900F00A
7.4.4.3 Transmit On receiving a bus request from the Link layer controller IC, the SIR72900F00A performs arbitration. When the SIR72900F00A wins the arbitration, it returns Grant ('11b') for one SCLK cycle and Idle for another SCLK cycle as Grant to the CTL pin of the Link layer controller IC Then the Link layer controller IC inputs Transmit ('10b') or Hold ('01b') to CTL and controls the PHY/LINK interface. However, to prevent data conflict on the CTL bus, the SIR72900F00A permits the Link layer controller IC to input Idle ('00b') for 1SCLK before inputting Transmit or Hold. (See Figure 7.22.) The Link layer controller IC can input Hold ('01b') to CTL to reserve the bus until the data to be transmitted is prepared, but the hold time must not exceed the MAX_HOLD time. Then it inputs Transmit ('10b) to CTL to show the valid range of the transmitted data.
www..com PHY Drive
CTL[0:1]
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
D[0:7]
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
Link Drive CTL[0:1] ZZ ZZ ZZ 00 01 01 10 10 10 10 00 00 ZZ
D[0:7]
ZZ
ZZ
ZZ
00
00
00
D0
D1
D2
Dn
00
00
ZZ
PHY Drive CTL[0:1] ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ 00
D[0:7]
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
00
Link Drive CTL[0:1] 10 10 01 00 ZZ ZZ ZZ ZZ 00 01 01 10 10
D[0:7]
Dn-1
Dn
SP
00
ZZ
ZZ
ZZ
ZZ
00
00
00
D0
D1
Figure 7.22 Transmit
Rev. 1.0
EPSON
39
S1R72900F00A
Having input the final bit of the packet data, the Link layer controller IC inputs Idle ('00b') or Hold ('01b') for one SCLK cycle and Idle for another SCLK cycle. Then the SIR72900F00A takes over the control of the PHY/LINK interface. This Hold ('01b') bit ensures that the Link layer controller IC transmits the next packet without giving up the serial bus (concatenated packet). On detecting a Hold bit, the SIR72900F00A outputs Transmit again to the CTL pin of the Link layer controller IC after the MIN_PACKET_SEPARATION time. The Link layer controller IC then transmits packets. The Hold operation is used to transmit a response packet after an Ack packet or to transmit multiple isochronous packets within the same isochronous cycle (subaction concatenation). In transmitting a Concatenated packet, the SIR72900F00A determines the Concatenated packet transmission speed according to the Enab_multi bit of PHY Register 5. When the Enab_multi bit is set to '0,' the SIR72900F00A recognizes that the transmission speed for the second and later packets is the same as that for the first packet.
www..com On the other
hand, when the Enab_multi bit is set to '1,' the SIR72900F00A recognizes the transmission speed for the Concatenated packet according to the SP value input to D while Hold ('01b') is being input to CTL.Table 7.12 shows the meaning of the SP value. However, the IEEE 1394 standards defines a transmission speed limit for Concatenated packets, prohibiting the transmission of a Concatenated packet at a speed of S100 after packet transmission at S200 or higher. To observe the speed limit, when the SIR72900F00A receives a request for 100-Mbps Concatenated packet transmission following a request for packet transmission at 200 Mbps or higher, it gives up the 1394 bus and performs arbitration in an attempt to transmit the 100-Mbps packet as a Single packet. Therefore, this 100-Mbps Concatenated packet transmission request from the Link layer controller IC will be handled as a bus request that occurs in ordinary LREQ, which may cause the IC to return CTL other than Grant (the request may be canceled). Packet transmission can be cancelled in the following two ways. After the Link layer controller IC takes control of the PHY/LINK interface, input Idle ('00b') for three SCLK cycles to give up the interface. Or, after the Link layer controller IC inputs Hold ('01b') to hold the bus, input Idle for two SCLK cycles to give up the interface. Empty packets are output to the serial bus.
7.4.4.4 Receive On receiving a packet, the SIR72900F00A outputs Receive ('10b') to the CTL pin, and 'H' to the D pin of the Link layer controller IC. Then the SIR72900F00A outputs a speed code (SP) to start packet data output. The SIR72900F00A continues to assert Receive ('10b') to the CTL terminal until the data reception completes. Then the SIR72900F00A asserts Idle ('00b') to declare that the packet reception has completed. As Receive operation, the SIR72900F00A outputs to the Link interface the Self-ID packets it transmits during the SelfID period. Also as Receive operation, the SIR72900F00A outputs to the Link interface, the response packets to the Extended PHY packet sent to the node. Once asserting Receive, the SIR72900F00A may terminate reception operation without outputting packet data. If the Link layer controller IC supports a transmission speed of 100 Mbps only, it must confirm the speed code (SP) to make sure that packet data received at 200 or 400 Mbps is ignored. If the Link layer controller IC supports transmission speeds of 100 and 200 Mbps only, it must confirm the speed code (SP) to make sure that packet data received at 400 Mbps is ignored.
40
EPSON
Rev. 1.0
S1R72900F00A
PHY Drive CTL[0:1] 00 10 10 10 10 10 10 10 10 00 00 00
D[0:7]
00
FF
FF
FF
FF
SP
D0
D1
Dn
00
00
00
Figure 7.23 Receive
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Table 7.15 Speed code (SP[0:7]) D[0:7] 00xxxxxxb 0100xxxxb 01010000b Data Rate 100Mbps 200Mbps 400Mbps
Rev. 1.0
EPSON
41
S1R72900F00A 7.5 Oscillating Circuit
The SIR72900F00A carries a built-in crystal oscillation circuit. The output frequency of the external quarts oscillator should be 24.576MHz ( 80ppm (including the temperature characteristics). As the quarts oscillator, we recommend our MA-406 (24.576MHz., CL = 10pF) to secure the necessary frequency precision. Position the quarts oscillator and capacitor in the neighborhood of this IC and maintain the wiring pattern as short as possible. Fig. 7.24 shows an example of external connection when using the MA-406. * The SIR72900F00A does not support external oscillator inputs.
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XO
XI
15pF
24.576MHz CL=10pF
15pF
Figure 7.24 Connection of external oscillating circuit
7.6 Power Down
The SIR72900F00A carries the power down mode. The power down mode can be obtained by inputting "1" into the PD pin and under the power down mode, all the internal functions will stop. The power down mode can be cancelled by changing the input to the PD pin from "1" to "0" and, a few ms (the time required for initialization) after the PD pin input became "0", normal operation will be restored.
42
EPSON
Rev. 1.0
S1R72900F00A
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Table 8.1 Absolute maximum ratings Item Operating voltage Input voltage Output voltage Output current/pin Storage temperatur Symbol VDD VIN VOUT IOUT TSTG Rating -0.3 to 4.0 -0.3 to VDD+0.5 -0.3 to VDD+0.5 30 -65 to 150 (VSS=0V) Unit V V V mA C
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8.2 Recommended Operating Conditions
Table 8.2 Recommended operating conditions Item Operating voltage Input voltage Operating temperature Symbol VDD VIN Ta Min. 3.00 VSS 0 Typ. 3.30 - - Max. 3.60 VDD 70 Unit V V C
Rev. 1.0
EPSON
43
S1R72900F00A 8.3 DC Characteristics
(AVDD, PVDD, OCSVDD, VDD=3.3V0.3V, Ta=0 to 70C) Item Symbol Condition Min. Typ. Max. Unit Power supply current (S400 packet transmission together with port 0.1) AVDD=3.6V PVDD=3.6V Supply current IDD 137 mA OSCVDD=3.6V VDD=3.6V Static current VIN=AVDD or PVDD www..com or OSCVDD or VDD or VSS Supply current IDDSA AVDD=4.0V 5.5 A PVDD=4.0V OCSVDD=4.0V VDD=4.0V Input leak Pin name: LREQ,CTL0,CTL1,D0 to 7,PD,LPS,BCLKON,XDIRECT,CPS,TPA*,TPB*,XRST,XI AVDD=3.6V PVDD=3.6V VDD=3.6V Input leak current IL VIH=AVDD, PVDD, -1 1 A OSCVDD, VDD VIL=AVDD, PVDD, OSCVDD, VDD Input characteristics (CMOS) Pin name: PD,PS1 to 3,XTEST_MODE,TEST0,TEST1 High level input voltage VIH VDD=3.6V 1.9 V Low level input voltage VIL VDD=3.0V 0.9 V Schmidt input characteristics 1 Pin name: XRST High level trigger voltage VT1+ VDD=3.6V 1.2 2.3 V Low level trigger voltage VT1- VDD=3.0V 0.7 1.7 V Schmidt input characteristics 2 Pin name: LREQ,CTL0,CTL1,D0 to 7,LPS High level trigger voltage VT2+ VDD=3.6V 2.1 2.7 V Low level trigger voltage VT2- VDD=3.0V 0.6 1.2 V CPS input characteristics Pin name: CPS High level trigger voltage VTCPS+ VDD=3.6V 1.36 2.0 V High level trigger voltage VTCPS- VDD=3.0V 1.16 1.68 V Input pull up characteristics Pin name: XRST VDD=3.0V 16.8 46.4 A Pull up resistor RPLU2 VIL=VSS
44
EPSON
Rev. 1.0
S1R72900F00A
Symbol Condition Min. Typ. Pin name: BNC VDD=3.0V VDD-0.4 High level output voltage VOH1 IOH=-2mA VDD=3.0V Low level output voltage VOL1 IOL=2mA Output characteristics 2 Pin name: BCLKON, SCLK, CTL0,CTL1, D0 to7 VDD=3.0V VDD-0.4 High level output voltage VOH2 IOH=-6mA VDD=3.0V Low level output voltage VOL2 IOL=6mA www..com Output characteristics 3 Pin name: SCLK,R1,TPBIAS1,TPBIAS2,FC1 VDD=3.6V Off-state leak current IOZ VOH=VDD -1 VOL=VSS Bus hold characteristics Pin name: LREQ,CTL0,CTL1, D0 to 7,LPS, VDD=3.0V -0.3 High level hold current IBHH VIN=2.6V VDD=3.0V Low level hold current IBHL VIN=0.4 VDD=3.6V High level drive current IBHHO IIL=-0.9mA VDD=3.6V VDD-0.4 Low level drive current IBHLO IIL=0.9mA Item Output characteristics 1 Max. Unit V 0.4 V
V 0.4 V
1
A
mA 0.3 VSS+0.4 mA V V
Rev. 1.0
EPSON
45
S1R72900F00A
Item Symbol Cable interface Common mode input voltage VIC Common mode input voltage VIC Common mode output voltage Common mode output current Common mode output current Common mode output current Differential input www..com voltage amplitude Differential output voltage amplitude Arb comparator threshold voltage (+) Arb comparator threshold voltage (-) S200 speed signal threshold voltage S400 speed signal threshold voltage BIAS detection threshold voltage Connection detection threshold voltage Cable power detection threshold voltage VOC IOCS1 IOCS2 IOCS4 Condition TPB cable input power supply node TPB cable input non-power supply node S100 S200 S400 Min. 1.03 0.523 1.665 -0.81 -4.84 -12.4 118 172 89 -168 VOC-273 VOC-701 0.6 0.6 5.9 1.85 Typ. Max. 2.015 2.515 2.015 0.44 -2.53 -8.1 265 265 168 -89 VOC-138 VOC-441 1 1 9.4 V mA mA mA mV mV mV mV mV mV V V V Unit V
46
EPSON
Rev. 1.0
S1R72900F00A 8.4 AC Characteristics
8.4.1 DC judgment level
VDD/2
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8.4.2 Clock timing
tscyc
SCLK tscc1 tscd
BCLKON TLINKON
Symbol tscyc tsccl tscd TLINKON
SCLK cycle SCLKHIGH pulse width SCLK LOW pulse width BCLKON cycle
Min. 20.343 9.16 9.16 125
Typ. 20.345
Max. 20.346 11.18 11.18 250
Unit ns ns ns ns
Rev. 1.0
EPSON
47
S1R72900F00A
8.4.3 PHY/LINK interface timing
SCLK
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TD
TD
TD
Output Timing CTL[0:1]
TD D[0:7]
TD
TD
TSU Intput Timing CTL[0:1]
TH
TSU D[0:7]
TH
Symbol TD TSU TH
CTL. D delay time CTL. D. LREQ setup time CTL. D. LREQ hold time
Min. 0.5 7 0
Typ. 1.9 18 1.3
Max. 13.5
Unit ns ns ns
8.4.4 Cable interface timing Symbol TTJITTER TTSKEW TTRF Min. -150 -100 0.5 Typ. Max. 150 100 1.2 Unit ps ps ns
TpA,TpB transmission jitter TpA/TpB transmission skew TpA/TpB rise time and fall time
48
EPSON
Rev. 1.0
S1R72900F00A
9. EXAMPLE OF EXTERNAL CONNECTION
0.1F
0.001F 0.001F
6.0k 1%
VDD TPBIAS
TPBIAS 1F TP Cables Interface Connection
1F TP Cables Interface Connection
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VDD 0.1F VDD 0.001F 0.001F
AVSS 48 TPBIAS1 47 TPA1_P 46 TPA1_N 45 TPB1_P 44 TPB1_N 43 AVDD 42 R1 41 R0 40 AVSS 39 TPBIAS0 38 TPA0_P 37 TPA0_N 36 TPB0_P 35 TPB0_N 34 AVSS 33
0.001F
0.1F 0.001F VDD
0.1F VDD 0.1F 0.001F 24.576MHz 15pF 5% 15pF 5% 0.001F 0.1F
1 LREQ 2 SCLK 3 BNC 4 CTL0 5 CTL1 6 D0 7 D1 8 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 PD 15 LPS 16 VDD
49 AVSS 50 AVSS 51 AVDD 52 AVDD 53 XRST 54 FC0 55 FC1 56 PVDD 57 PVSS 58 OSCVSS 59 XI 60 XO 61 OSCVDD 62 VDD 63 VSS 64 VSS
S1R72900F00A
AVSS 32 AVDD 31 AVDD 30 TEST1 29 TEST0 28 XTET_MODE 27 VDD 26 VDD 25 CPS 24 DIRECT 23 PS0 22 PS1 21 PS2 20 BCLKON 19 VSS 18 VSS 17
1k 0.001F 0.001F Cable Power VDD 0.1F Vss
240k
DIRECT VDD Power-Class Programing Bus Manager 10k LKON
Rev. 1.0
EPSON
Power Down Link Pulse or VDD Link VDD
BNC Out
VDD
0.1F
49
S1R72900F00A
10. OUTLINE DIMENSIONS
Plastic QFP13-64 pin
12-0.4 10-0.1
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48
33
49
32
INDEX 64 17
1
1.4-0.1
16 0.5 0.18 -0.05 0.125 +0.05 -0.025 0
+0.1
1.7Max.
10-0.1 0.1
10 0.5 1
-0.2
12-0.4
Unit:mm
50
EPSON
Rev. 1.0
International Sales Operations
AMERICA
EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS
150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone : +1-408-922-0200 Fax : +1-408-922-0238
ASIA
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone : 64106655 Fax : 64107319
SHANGHAI BRANCH SALES OFFICES West
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EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone : +852-2585-4600 Fax : +852-2827-4346 Telex : 65542 EPSCO HX
Central www..com
101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone : +1-815-455-7630 Fax : +1-815-455-7633
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
10F, No. 287,Nanking East Road, Sec. 3 Taipei Phone : 02-2717-7360 Fax : 02-2712-9164 Telex : 24444 EPSONTB
Northeast
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Southeast
3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. Phone : +1-877-EEA-0020 Fax : +1-770-777-2637
HSINCHU OFFICE
13F-3, No.295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone : 03-573-9900 Fax : 03-573-9169
EUROPE
EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS
Riesstrasse 15 80992 Munich, GERMANY Phone : +49- (0) 89-14005-0 Fax : +49- (0) 89-14005-110
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone : +65-337-7911 Fax : +65-334-2716
SEIKO EPSON CORPORATION KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone : 02-784-6027 Fax : 02-767-3677
SALES OFFICE
Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone : +49- (0) 2171-5045-0 Fax : +49- (0) 2171-5045-10
SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone : +44- (0) 1344-381700 Fax : +44- (0) 1344-381701
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone : +33- (0) 1-64862350 Fax : +33- (0) 1-64862355
ED International Marketing Department Europe & U.S.A.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564
BARCELONA BRANCH OFFICE Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone : +34-93-544-2490 Fax: +34-93-544-2491
ED International Marketing Department Asia
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110
In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings.
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S1R72900F00A
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
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First issue September,2001 Printed in Japan H A

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